An operating system for a multiprocessor environment can have several processes that are common code elements used by all processors. Similarly, several processes may share common data sets used by all processors. In a multiprocessor system having a “write-into-cache” architecture, gatewords are used in a software controlled process to prevent more than one processor from executing common code or accessing shared data at the same time. A unique gateword that is assigned to a given process or data set is tested to assure that no other processor is currently executing or accessing the information a given processor is requesting. This procedure prevents a detrimental activity from occurring when a processor changes data at the same time another processor is using it.
In a write-into-cache architecture, the gateword (stored in a main memory before startup or before a climb to another job) for given code or data is transferred from one processor to another while testing for the gateword to be OPENed (made available). This requires data siphoning between caches. The siphoning process introduces significant delays when the copied data must be siphoned through multiple levels of cache. Thus, in modern multiprocessing systems, not all processors are equal when it comes to data siphoning delays. The more cache mechanisms a given gateword must pass through, the longer it will take the gateword to arrive at the requesting processor.
A process decision cannot be made until a siphoned gateword arrives and can be tested by a processor seeking access to the code/data guarded by the gateword. The delays can be sufficiently excessive as to prevent a processor with long siphon delays in a given condition from timely acquiring the relevant gateword before another processor has overwritten (and thus “Closed”) it. This undesirable result is commonly called “hogging”.
Different schemes to work around the hogging problem use software delays before the gateword is retested, but these delays are made without any assurance that a processor board (carrying a plurality of CPUs) that currently retains the gateword will relinquish access to a CPU on another, “gateword-starved”, board. Other schemes use interrupts to broadcast the identity of the processor board that currently has control of the gateword so that CPUs on the same board will detect this and then delay longer, giving CPUs on another board (gateword starved board) a chance to access the gateword. Still other mechanisms use a dedicated processor to maintain a gateword queue, while yet other systems devote hardware in the form of FIFO arrays or fast logic across board boundaries in attempts to create equal access in a multiprocessor environment.
Software systems have typically relied on hardware to mediate the gateword access controls using a read-alter-rewrite method of access. Specific gate handling instructions used this mechanism which was satisfactory when processors in a multiprocessor system had substantially the same access times within the context of processor clock speeds. But, as hardware designs became more complex and processor speeds increased, it also became more difficult to attain the interface speeds necessary to handle the gateword access priority without a system performance penalty. The responsibility for access to heavily used gatewords has gradually become more dependent on software mechanisms as software designers become increasingly aware of the problems that can occur as a result of the hogging effect.
Most software techniques employed to handle the hogging problem are of fixed delay types that will always delay access to a gateword whether a delay is required or not. Fixed delay techniques significantly reduce system performance, and this type of software technique must be tuned to the system architecture and may even have to be tuned to various gates within the operating system.
One highly effective solution (essentially different from the solution provided by the present invention) for the hogging problem is disclosed and claimed in copending application Ser. No. 10/219,644, filed Aug. 15, 2002, entitled: “Gateword Acquisition in a Multiprocessor Write-Into-Cache Environment”, owned by the same assignee as the present application and which issued as U.S. Pat. No. 6,760,811 on Jul. 6, 2004.
The solution set forth in application Ser. No. 10/219,644, however, requires the creation of at least one, and typically two, new operating system instructions. This requirement has certain potential drawbacks. Programmers must be informed about and understand the use of the new commands. Legacy software must be revised to include the command(s) in order to enjoy the anti-hogging benefits. There may not be sufficient unused operation codes in the instruction set, or even in the hardware, to accommodate the new instructions.
Another highly effective solution (also essentially different from the solution provided by the present invention and from the invention of the application mentioned immediately above) for the hogging problem is disclosed and claimed in copending application Ser. No. 10/256,289 filed Sep. 26, 2002, entitled: “Balanced Access to Prevent Gateword Dominance in a Multiprocessor Write-Into-Cache Environment”, owned by the same assignee as the present application and which issued as U.S. Pat. No 6,868,483 on Mar. 15, 2005. In the solution set forth in Application Ser. No. 10/256,289, each processor includes a gate control flag. A gateword CLOSE command, establishes ownership of the gateword in one processor and prevents other processors from accessing the code/data guarded until the one processor has completed its use. A gateword OPEN command then broadcasts a gateword interrupt to set the flag in each processor, delays long enough to ensure that the flags have all been set, writes an OPEN value into the gateword and flushes the gateword to main memory. A gateword access command executed by a requesting processor checks its gate control flag, and if set, starts a fixed time delay after which normal execution continues. This solution to the hogging problem involves the addition of a flag in each processor and revision of OPEN and gateword access commands, and there may not be space in the hardware and/or instruction set to implement this solution.
Accordingly, it would be highly desirable to provide hardware assistance in effecting software handling of gateword control in a complex multiple processor system with a write-into-cache architecture which, however, provides equal access, directly from a main memory, by all processors to a gateword stored and maintained in the main memory. Further, it would be highly desirable to achieve this end in a manner which can be readily adapted to all multiprocessor architectures. The present invention achieves these objectives in a relatively simple and highly effective manner.